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description 32171 group is a 32-bit, single-chip risc microcomputer with built-in flash memory, which was developed for use in general industrial and household equipment. to make full use of microcomputer built-in mass volume flash memory, this microcomputer contains a variety of pe- ripheral functions ranging from two independent blocks of 16-channel a-d converters to 37-channel multifunction tim- ers, 10-channel dmas, 3-channel serial i/os, and 1-channel real time debugger. also included 1-channel full-can mod- ules and jtag (boundary scan facility). with lower power consumption and low noise characteristics also considered, these microcomputers are ideal for embed- ded equipment applications. features m32r risc cpu core ? uses the m32r family risc cpu core (instruction set common to all microcomputers in the m32r family) ? five-stage pipelined processing ? sixteen 32-bit general-purpose registers ? 16-bit/32-bit instructions implemented ? dsp function instructions (sum-of-products calculation using 56-bit accumulator) ? built-in flash memory ? built-in flash programming boot program ? built-in ram ? pll clock generating circuit .............. built-in 4 pll circuit ? maximum operating frequency of the cpu clock 40mhz(when operating at -40 to +85 o c) 32mhz(when operating at -40 to +125 o c) table 1 type name list (32171 group) type name ram size rom size M32171F4VFP 16k bytes 512k bytes m32171f3vfp 16k bytes 384k bytes m32171f2vfp 16k bytes 256k bytes 37-channel multijunction timers (mjt) multifunction timers are incorporated that support various purposes of use. 16-bit output related timers ....................................... 35ch 16-bit input/output related timers .............................. 10ch 16-bit input related timers ........................................... 8ch 32-bit input related timers ........................................... 8ch ? flexible configuration is possible through interconnection of timers. ? the internal dmac and a-d converter can be started by a timer. real-time debugger ? includes dedicated clock-synchronized serial i/o that can read and write the contents of the internalram indepen- dently of the cpu. ? can look up and update the data table in real time while the program is running. ? can generate a dedicated interrupt based on rtd commu- nication. abundant internal peripheral functions in addition to the timers and real-time debugger, the microcomputer contains the following peripheral functions. ? dmac ............................................................ 10 channels ? a-d converter .................... 10-bit converter 16 channels ? serial i/o ........................................................... 3 channels ? interrupt controller ......... 22 interrupt sources, 8 priority levels ? wait controller ? full can ............................................................ 1 channel ? jtag (boundary scan function, mitsubishi original) designed to operate at high temperatures to meet the need for use at high temperatures, the micro- computer is designed to be able to operate in the temperature range of -40 to +125 o c when cpu clock operating frequency = 32 mhz. when cpu clock operating frequency = 40 mhz, the microcomputer can be used in the temperature range of -40 to +85 o c. note: this does not guarantee continuous operation at 125 o c. if you are considering use of the microcom puter at 125 o c, please consult mitsubishi. applications automobile equipment control (e.g., engine, abs, at), indus- trial equipment system control, and high-function oa equip- ment (e.g., ppc) mitsubishi microcomputers single-chip 32-bit cmos microcomputer 32171 group 2001-5-14 rev.1.0
mitsubishi microcomputers 2 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group figure 1 pin layout diagram of the m32171 pin assignment(top view) package 144p6q-a 44 43 37 38 39 40 41 42 60 59 51 52 53 54 55 56 45 46 47 48 49 50 57 58 63 64 66 67 68 69 70 71 72 65 61 62 8 9 90 99 98 97 96 95 9 4 9 3 9 2 9 1 1 03 1 02 1 01 10 8 10 7 10 6 1 05 1 04 73 7 4 84 75 7 6 77 7 8 79 8 0 81 82 83 85 86 8 7 88 1 00 2 4 3 5 6 7 8 9 3 5 22 23 24 25 2 6 27 2 8 29 30 31 32 33 34 11 1 2 13 14 15 16 17 1 8 1 9 20 21 1 0 1 36 p43/ rd vss vcci p41/ blw / ble p153/tin3 p150/tin0 vcce p107/to15 p106/to14 p104/to12 p103/to11 vcci p42/ bhw / bhe p125/tclk1 p124/tclk 0 v cnt o sc-vcc xout x in osc-vs s p37 /a22 p3 6/a2 1 p33 /a1 8 p31 /a1 6 p30 /a1 5 p3 5/a2 0 p34/ a 19 p32 /a1 7 p 2 7 / a 3 0 p 2 5 / a2 8 p2 6/a29 p24/a2 7 p11/ db9 p07/ db7 p0 5/db5 p02/db 2 p0 1/db 1 p00 / db0 p 2 3 / a2 6 p 22 /a2 5 p 20 /a23 p10 / db8 p 0 6/d b6 p0 4/db4 p03/ db3 p 21 /a2 4 p44/ cs0 p45/ cs1 p47/a14 p46/a13 p 22 1/c rx p14/db12 p15/db13 p16/db14 p17/db 15 p82/txd0 p83/rxd0 p174/txd2 p175/rxd2 vss vcci vref0 avcc0 ad0in7 ad0in6 ad0in5 ad0in4 ad0in3 ad0in2 ad0in1 ad0in0 ad0in15 ad0in14 ad0in13 ad0in12 ad0in11 ad0in10 ad0in9 ad0in8 avss0 p85/txd1 p86/rx d1 res et p87/sclki1/sclko1 vss p6 2 f p p9 4/to17 p7 4/rt dtxd p75/ rt drx d p 7 6/r t d a ck p77/rt dclk p61 p 6 3 p 11 4/t o4 p11 5/to5 p 11 6/t o6 p1 17/to7 vcce mod 1 p 11 2/t o2 p11 3/t o3 p7 0 / b c l k / w r p71/ wa it p72/ hre q p6 4/ sbi mod0 p9 3 / t o 1 6 p 7 3 / ha ck v dd f v cc vs s p127/tclk 3 p100 /t o8 p1 01/to9 p 10 2/t o10 p137/tin2 3 p136/tin2 2 p135/tin2 1 p134/tin2 0 p105/to 13 p110 /to0 p 111 /t o 1 p97/ to20 p96/to 19 p9 5/to18 p133/tin1 9 p132/tin1 8 p131/tin1 7 p130/tin1 6 p126/tclk 2 jtdi jtdo jtr st jtck jt ms p 1 2 / db 1 0 p84/sclki0/sclko0 vc ce vc ce 112 119 116 115 113 111 110 109 120 117 114 124 132 130 129 127 121 137 144 143 142 141 140 139 138 133 136 135 134 123 122 131 128 125 126 118 p220/ct x p2 25 /a12 p13/db 11 vs s M32171F4VFP m32171f3vfp m32171f2vfp
mitsubishi microcomputers 3 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group figure 2 block diagram pll clock generation circuit internal bus interface address data internal ram (16kb ) internal flash memory (M32171F4VFP : 512kb) (m32171f3vfp : 384kb) (m32171f2vfp : 256kb) m32r cpu core (max 40mhz) multiplier- accumulator (32 16 + 56) dmac (10 channels) multijunction timer (mjt : 37 channels) serial i/o (3 channels) a-d converter (10-bit, 16 channels) wait controller interrupt controller (22 sources, 8 levels) real-time debugger (rtd) external bus interface internal 16-bit bus internal 32-bit bus input/output port(jtag) 97 lines full can (1 channel) 32171
mitsubishi microcomputers 4 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group table 2 outline performance (1/2) functional block features m32r cpu core m32r family cpu core, internally configured in 32 bits built-in multiplier-accumulator (32 16 + 56) basic bus cycle : 25 ns (cpu clock frequency at 40 mhz, internal peripheral clock frequency at 20 mhz) logical address space : 4g bytes, linear general-purpose register : 32-bit register 16, control register: 32-bit register 5 accumulator : 56 bits external data bus 16 bits data bus instruction set 16-bit/32-bit instruction formats 83 instructions/ 9 addressing modes internal flash memory M32171F4VFP : 512k bytes m32171f3vfp : 384k bytes m32171f2vfp : 256k bytes rewrite durability : 100 times internal ram 16k bytes dmac 10 channels (dma transfers between internal peripheral i/os, between internal peripheral i/o and internal ram, and between internal rams) channels can be cascaded and can operate in combination with internal peripheral i/o multijunction timer 37 channels of multijunction timers ? 16-bit output-related timers 11 channels (single-shot, delayed single-shot) ? 16-bit input/output-related timers 10 channels (event count mode, single-shot, pwm, measurement) ? 16-bit input-related timers 8 channels (measurement, event count mode) ? 32-bit input-related timers 8 channels (measurement) flexible timer configuration is possible through interconnection of channels using the event bus. a-d converter 10-bit multifunction a-d converters ? input 16 channels ? scan-based conversion can be switched with 4, 8, and 16 ? capable of interrupt conversion during scan ? 8-bit/10-bit readout function available serial i/o 3 channels (the serial i/os can be set for synchronous serial i/o or uart. sio2 is uart mode only) real-time debugger (rtd) 1-channels dedicated clock-synchronized serial ? the entire internal ram can be read or rewritten from the outside without cpu intervention interrupt controller controls interrupts from internal peripheral i/os (priority can be set to one of 8 levels including interrupt disabled) wait controller controls wait when accessing external extended area (1 to 4 wait cycles inserted + prolonged by external wait signal input) can 16-channels message slots jtag boundary-scan function
mitsubishi microcomputers 5 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group table 1 outline performance (2/2) function block features clock maximum internal cpu memory clock : 40mhz (access to cpu, internal rom, andinternal ram) maximum internal peripheral clock : 20mhz (access to internal peripheral module) maximum external input clock : 10.0mhz, built-in multiply-by-4 pll circuit power supply voltage external i/o : 5v ( 0.5v) or 3.3v ( 0.3v) internal logic : 3.3v ( 0.3v) operating temperature rang -40 to +125 c (cpu memory clock 32mhz , internal peripheral clock 16mhz) -40 to +85 c (cpu memory clock 40mhz , internal peripheral clock 20mhz) package 0.5mm pitches / 144-pin plastic lqfp
mitsubishi microcomputers 6 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group outline of the cpu core the m32171 group uses the m32r risc cpu core, and has an instruction set which is common to all microcomputers in the m32r family. instructions are processed in five pipelined stages consisting of instruction fetch, decode, execution, memory access, and write back. thanks to its out-of-order-completion mechanism, the m32r cpu allows for clock cycle efficient, instruction ex- ecution control. the m32r cpu internally has sixteen 32-bit general-purpose registers. the instruction set consists of 83 discrete instruc- tions, which come in either a 16-bit instruction or a 32-bit in- struction format. use of the 16-bit instruction format helps to reduce the code size of a program. also, the availability of 32- bit instructions facilitates programming and increases the per- formance at the same clock speed, as compared to architectures with segmented address spaces. sum-of-products instructions comparable to dsp the m32r cpu contains a multiplier/accumulator that can execute 32 bits 16 bits in one cycle. therefore, it executes a 32 bit 32 bit integer multiplication instruction in three cycles. also, the m32r cpu supports the following four sum-of-prod- ucts instructions (or multiplication instructions) for dsp func- tion use. (1) 16 high-order register bits 16 high-order register bits (2) 16 low-order register bits 16 low-order register bits (3) all 32 register bits 16 high-order register bits (4) all 32 register bits 16 low-order register bits furthermore, the m32r cpu has instructions for rounding the value stored in the accumulator to 16 or 32 bits, and instruc- tions for shifting the accumulator value to adjust digits before storing in a register. because these instructions also can be executed in one cycle, dsp comparable data processing ca- pability can be obtained by using them in combination with high-speed data transfer instructions such as load & address update or store & address update. three operation modes the m32170 and m32174 group has three operation modes: single-chip mode, external extended mode, and processor mode. these operation modes are changed from one to an- other by setting the mod0 and mod1 pins. address space the m32171 groups logical addresses are always handled in 32 bits, providing 4 gbytes of linear address space. the m32171 groups address space consists of the following. user space a 2-gbyte area from h0000 0000 to h7fff ffff is the user space. located in this space are the user rom area, external extended area, internal ram area, and sfr (special func- tion register) area (internal peripheral i/o registers). of these, the user rom area and external extended area are lo- cated differently depending on mode settings. boot program space a 1-gbyte area from h8000 0000 to hbfff ffff is the boot program area. this space contains the on-board program- ming program (boot program) used in blank state by the inter- nal flash memory. system space a 1-gbyte area from hc000 0000 to hffff ffff is the system area. this space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user.
mitsubishi microcomputers 7 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group figure 3 pin function diagram of 240qfp xin reset m3 2171f 4vfp, m32171 f3vfp, m32171f 2vfp clock reset vcci vs s 3 5 p20-p27 / a23-a30 p30-p37 / a15-a22 p46, p47 / a13, a 14 p225 / a12 address bus 19 data bus 16 p72 / hreq p73 / hack bus control p71 / wai t interrupt controller p43 / r d p44 / c s0 p45 / c s1 p41 / blw / b le p42 / bhw / b he port 2 port 3 port 4 port 22 port 0 port 1 port 7 port 4 xout vc nt osc-vc c osc-vs s mo d0 mo d1 mode p150,p153 / tin0,tin3 p130-p137 / tin16-tin23 10 port 15 port 13 p124-p127 / tclk0-tclk3 4 multijunction timer 21 p100-p107 / to8-to15 p110-p117 / to0-to7 port 12 port 11 port 10 port 9 p74 / rtdtxd p75 / rtdrxd p76 / rtdack p77 / rtdcl k real-time debugger port 7 p70 / bclk / w r port 7 p82 / txd 0 p83 / rxd 0 p84 / sclki 0 / sclko 0 p85 / txd 1 p86 / rxd 1 p87 / sclki 1 / sclko 1 serial i/o port 8 a-d converter avcc 0 p61-p63 port 6 vref 0 vdd fvcc fp vc ce 4 p174 / txd 2 p175 / rxd2 port 17 3.3v (note) 5v 3.3v 5v 3. 3v 3.3v 5v note: : operates with a 3.3v power supply. : operates with a 5v or 3.3v power supply. 16 ad0in0a-d0in15 p220 / c tx p221 / c rx can jtms jtck jtrst jt do jt ag jt di port 22 p64 / s bi port 6 avss 0 p93-p97 / to16-to720 p00-p07 / db0-db7 p10-p17 / db8-db15
mitsubishi microcomputers 8 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group table 4 description of pin function (1/4 ) type pin name description input/output function power vcce power supply supplies power (5 v or 3.3v) to external i/o ports. supply vcci power supply supplies power (3.3 v) to the internal logic. vdd ram power supply nternal ram backup power supply (3.3 v). fvcc fl ash power supply internal flash memory backup power supply (3.3 v). vss ground connect all vss pins to ground (gnd). clock xin, clock input clock input/output pins. these pins contain a pll-based xout output frequency multiply-by-4, so input the clock whose frequency is quarter the operating frequency. (xin input = 10 mhz when cpu clock operates at 40 mhz) bclk / system clock output when this signal is system clock(bclk), it outputs a clock whose is twice that of ______ wr external inpout clock. (bclk output = 20 mhz when cpu clock operates at 40 mhz). use this clock when circuits are synchronized externally. ______ when this signal is write(wr), during external write access it indicates the valid data on the data bus to transfer. osc-vcc power supply power supply to the pll circuit. connect osc-vcc to the power supply(3.3v) osc-vss ground connect osc-vss to ground. vcnt pll control input this pin controls the pll circuit. connect a resistor and capacitor to this pin. reset ______ reset reset input this pin resets the internal circuits. mode mod0 mode input these pins set an operation mode. mod1 mod0 mod1 mode 0 0 single-chip mode 0 1 expanded external mode 1 0 processor mode 0 0 (boot mode) (note) 1 1 (reserved) address a12-a30 address output 19 lines of address bus (a12-a30) are provided to accommodate two bus bus channels of 1 mb memory space (max.) connected external to the chip. a31 is not output. in the write cycle, of the 16-bit data bus the valid byte positions to write are _________ ________ ________ _______ output as bhw/ bhe and blw/ ble. in read cycle, data on the entire 16-bit data bus is read. however, only the data at the valid byte positions are transferred to the m32rs internal circuit. data bus db0-db15 data bus input/output this 16-bit data bus connects to external device. note: fp pin should be h level in boot mode.
mitsubishi microcomputers 9 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group table 5 description of pin function (2/4) type pin type description input/output function bus ___ cs0, chip output chip select signals for external devices. control cs1 select __ rd read output this signal is output when reading external devices. ___ _______ bhw/ bhe byte high output indicates the byte positions to which valid are transferred when writing to write ________ _______ ________ _______ external devices.bhw/ bhe and blw/ ble correspond to the upper address ___ _______ blw/ ble byte low output side(d0-d7 effective) and the lower address side(d8-d15 effective),respectivel. write ____ wait wait input _________ if wait input is low when the m32r accesses external devices, the wait cycle extended. _____ hreq hold input this pin is used by an external device to request control of the external bus. request __________ the m32r goes to a hold state when hreq input is pulled low. ____ hack hold output this signal indicates to the external device that the m32r has entered a hold acknowledge state and relinquished control of the external bus. multijunction tin0, tin3 timer input input input pins for multijunction timer. timer tin16-tin23 to0 timer output output output pins for multijunction timer. -to20 tclk0 timer clock input clock input pins for multijunction timer. -tclk3 a-d avcc0, analog power C avcc0 is the power supply for the a-d0 converters.connect avcc0 converter upply to the power supply (5v or 3.3v). avss0 analog groundC avss0 is the analog ground for the a-d0 converters. connect avcc0 to ground ad0in0 analog input input 16-channel analog input pin for a-d0 converter. -ad0in15 vref0 reference input vref0 is the reference voltage input pin (5v or 3.3v) for the a-d0 converters. voltage input interrupt ___ sbi system input system break interrupt(sbi) input pin of the interrupt controller. controller break interrupt
mitsubishi microcomputers 10 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group table 6 description of pin functions (3/4) type pin name description input/output function serial sclki0/ uart transmit/ input/output when channel 0 is in uart mode: i/o sclko0 receive clock clock output derived from brg output by dividing it by 2 output or csio transmit/receive when channel 0 is in csio mode: clock transmit/receive clock input when external clock is selected input/output transmit/receive clock output when internal clock is selected sclki1/ uart transmit/ input/output when channel 1 is in uart mode: sclko1 receive clock clock output derived from brg output by dividing it by 2 output or csio transmit/receive when channel 1 is in csio mode: clock transmit/receive clock input when external clock is selected input/output transmit/receive clock output when internal clock is selected txd0 transmit data output transmit data output pin for serial i/o channel 0 rxd0 receive data input receive data input pin for serial i/o channel 0 txd1 transmit data output transmit data output pin for serial i/o channel 1 rxd1 receive data input receive data input pin for serial i/o channel 1 txd2 transmit data output transmit data output pin for serial i/o channel 2 rxd2 receive data input receive data input pin for serial i/o channel 2 real-time rtdtxd transmit data output serial data output pin of the real-time debugger debugger rtdrxd receive data input serial data input pin of the real-time debugger rtdclk clock input input serial data transmit/receive clock input pin of the real-time debugger rtdack acknowledge output this pin outputs a low pulse synchronously with the real-time debuggers first clock of serial data output word. the low pulse width indicates the type of the command/data the realtime debugger has received. flash- fp flash protect input this pin protects the flash memory against e/w in hardware. only can ctx transmit data output data output pin from can module. crx receive data input data input pin to can module. jtag jtms test mode input test select input for controlling the test circuits state transition jtck clock input clock input to the debugger module and test circuit. jtrst test reset input test reset input for initializing the test circuit asynchronously. jtdo serial output output serial output of test instruction code or test data. jtdi serial input input serial input of test instruction code or test data.
mitsubishi microcomputers 11 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group table 7 description of pin functions (4/4) type pin name description input/output function p00-p07 input/output port 0 input/output programmable input/output port. p10-p17 input/output port 1 input/output programmable input/output port. p20-p27 input/output port 2 input/output programmable input/output port. p30-p37 input/output port 3 input/output programmable input/output port. p41-p47 input/output port 4 input/output programmable input/output port. p61-p64 input/output port 6 input/output programmable input/output port. (however, p64 is an input-only port) p70-p77 input/output port 7 input/output programmable input/output port. p82-p87 input/output port 8 input/output programmable input/output port. p93-p97 input/output port 9 input/output programmable input/output port. p100 input/output port 10 input/output programmable input/output port. -p107 p110 input/output port 11 input/output programmable input/output port. -p117 p124 input/output port1 2 input/output programmable input/output port. -p127 p130 input/output port 13 input/output programmable input/output port. -p137 p150, p153 input/output port 15 input/output programmable input/output port. p174, p175 input/output port 17 input/output programmable input/output port. p220, input/output port 22 input/output programmable input/output port. p221, p225 (however, p221 is an input-only port) note: input/output port 5 is reserved for future use. input/output ports 14, 16, 18, 19, 20, and 21 do not exist. input/ output port (note)
mitsubishi microcomputers 12 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group figure 4 address space of the M32171F4VFP boot rom area (8k bytes) h'0000 0000 h'ffff ffff < logical space of the M32171F4VFP > h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16m bytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16k bytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 user rom area expanded external area (4m bytes) ghost area in units of 128k bytes 1g bytes 1g bytes 2g bytes ghost area in units of 16m bytes ghost area in units of 4m bytes internal ram (16k bytes) h'0080 7fff h'8000 0000 h'8000 1fff ghost area in units of 16k bytes reserved area (8k bytes) reserved area (96k bytes) h'0081 ffff h'0082 0000 h'0080 8000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'0007 ffff h'0010 0000 cs1 area cs0 area reserved area (512k bytes) h'000f ffff ghost area in cs1 (1m byte) h'002f ffff h'0030 0000
mitsubishi microcomputers 13 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group figure 5 address space of the m32171f3vfp boot rom area (8k bytes) h'0000 0000 h'ffff ffff < logical space of the m32171f3vfp > h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16m bytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16k bytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 user rom area expanded external area (4m bytes) ghost area in units of 128k bytes 1g bytes 1g bytes 2g bytes ghost area in units of 16m bytes ghost area in units of 4m bytes internal ram (16k bytes) h'0080 7fff h'8000 0000 h'8000 1fff ghost area in units of 16k bytes reserved area (8k bytes) reserved area (96k bytes) h'0081 ffff h'0082 0000 h'0080 8000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'0005 ffff h'0010 0000 cs1 area cs0 area reserved area (640k bytes) h'000f ffff ghost area in cs1 (1m byte) h'002f ffff h'0030 0000
mitsubishi microcomputers 14 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group figure 6 address space of the m32171f2vfp boot rom area (8k bytes) h'0000 0000 h'ffff ffff < logical space of the m32171f2vfp > h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16m bytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16k bytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 user rom area expanded external area (4m bytes) ghost area in units of 128k bytes 1g bytes 1g bytes 2g bytes ghost area in units of 16m bytes ghost area in units of 4m bytes internal ram (16k bytes) h'0080 7fff h'8000 0000 h'8000 1fff ghost area in units of 16k bytes reserved area (8k bytes) reserved area (96k bytes) h'0081 ffff h'0082 0000 h'0080 8000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'0003 ffff h'0010 0000 cs1 area cs0 area reserved area (768k bytes) h'000f ffff ghost area in cs1 (1m byte) h'002f ffff h'0030 0000
mitsubishi microcomputers 15 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group figure 7 sfr area h'0080 0000 h'0080 007e h'0080 0180 h'0080 0080 a-d converter h'0080 00ee serial i/o h'0080 0100 h'0080 0146 wait controller mjt (common part) mjt (top) h'0080 0200 h'0080 0240 h'0080 0300 h'0080 03c0 h'0080 03e0 h'0080 03f e note: the real-time debugger (rtd) is an independent module operated from external circuits, and is transparent to the cpu. +0 address +1 address 0 7 8 15 to to to to to to to to +0 address +1 address 0 7 8 15 multijunction timer (mjt) flash control h'0080 07e0 h'0080 07f2 h'0080 023e h'0080 02fe h'0080 0400 dmac h'0080 047e to mjt (tml1) h'0080 0fe0 h'0080 0ffe h'0080 0700 input/output ports h'0080 0756 to h'0080 03be h'0080 03d8 to to can h'0080 1000 h'0080 11fe to h'0080 3ffe interrupt controller (icu) mjt (tio) mjt (tms) mjt (tml0)
mitsubishi microcomputers 16 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group built-in flash memory and ram the M32171F4VFP contains 512-kbyte flash memory and 16-kbyte ram. the m32171f3vfp contains 384-kbyte flash memory and 16-kbyte ram. the m32171f2vfp con- tains 256-kbyte flash memory and 16-kbyte ram. the internal flash memory can be programmed on-board (i.e., while being mounted on the printed circuit board). this means that the same chip as will be used in mass-produc- tion can be used directly from the development stage on, allowing for system development without having to change the printed circuit board when proceeding from trial produc- tion to mass-production. built-in virtual-flash emulation function internal flash memory, which is divided from the first address in units of 8 kbyte (l banks), can be replaced in 8 -kbyte blocks (h70080 4000-h0080 5fff) from the beginning of the internal ram. and also the internal flash memory, which is divided from the first address in units of 4-kbyte area (all s banks), can be replaced within two 4 kbytes areas (h0080 6000-h0080 7fff). this function allows parts of the program which are fre- quently changed during development to be altered or evalu- ated without having to reset the microcomputer each time. whats more, when combined with the realtime debugger, this function helps to reduce the program evaluation period, because data in the ram can be rewritten without requiring any cpu load. figure 8 virtual-flash emulation areas of the M32171F4VFP (replaced in units of 8 kbytes) note 1: if the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is ena bled, the corresponding internal ram area is assigned to either bank register according to the priority felbank0 > fesban k0 > fesbank1. note 2: when access is made to the 8-kbyte area (l bank) specified with pseudo-flash bank register 0, the internal ram area is accessed. during pseudo-flash emulation mode, ram data can read and written to and from both the internal r am area and the virtual-flash setup area. h'0000 0000 h'0000 2000 < internal flash > < internal ram > h'0080 4000 h'0080 5ff f h'0000 4 000 8k bytes h'0000 1fff h'0000 3fff h'0000 5ff f h'0007 e000 h'0007 ffff h'0007 c000 h'0007 dff f 4k bytes h'0080 6000 h'0080 7fff l bank 0 (8k bytes) l bank 1 (8k bytes) l bank 2 (8k bytes) l bank 62 (8k bytes) l bank 63 (8k bytes) 4k bytes
mitsubishi microcomputers 17 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group figure 9 virtual-flash emulation areas of the M32171F4VFP (replaced in units of 4 kbytes) note 1: if the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is ena bled, the corresponding internal ram area is assigned to either bank register according to the priority felbank0 > fesban k0 > fesbank1. note 2: when access is made to the 4-kbyte area (s bank) specified with virtual-flash bank registers 0 and 1, the internal ram area is accessed. during virtual-flash emulation mode, ram data can read and written to and from both the internal ram area and the virtual-flash setup area. h'0000 0000 h'0000 1000 < internal flash > < internal ram> h'0080 4000 h'0080 5ff f h'0000 2 000 h'0000 0fff h'0000 1fff h'0000 2ff f h'0007 f000 h'0007 ffff h'0007 e000 h'0007 efff h'0080 6000 h'0080 7000 s bank 0 (4k bytes) s bank 1 (4k bytes) s bank 2 (4k bytes) s bank 126 (4k bytes) s bank 127 (4k bytes) 8k bytes 4k bytes 4k bytes virtual-flash emulation areas of M32171F4VFP, m32171f3vfp, and m32171f2vfp are shown as follows. table 8 virtual-flash emulation areas type name virtual-flash emulation areas M32171F4VFP h 0000 0000 - h 0007 ffff m32171f3vfp h 0000 0000 - h 0005 ffff m32171f2vfp h 0000 0000 - h 0003 ffff
mitsubishi microcomputers 18 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group input/output ports the microcomputer has a total of 97 input/output ports p0-p22. (however, p5 is reserved for future use, p14, p16, and p18-p21 do not exist.) the input/output ports can be used as input ports or output ports by setting uptheir direction registers. table 9 outline of input/output ports item specification number of port total 97 ports p0 : p00 - p07 (8 lines) p1 : p10 - p17 (8 lines) p2 : p20 - p27 (8 lines) p3 : p30 - p37 (8 lines) p4 : p41 - p47 (7 lines) p6 : p61 - p64 (4 lines) p7 : p70 - p77 (8 lines) p8 : p82 - p87 (6 lines) p9 : p93 - p97 (5 lines) p10 : p100 - p107 (8 lines) p11 : p110 - p117 (8 lines) p12 : p124 - p127 (4 lines) p13 : p130 - p137 (8 lines) p15 : p150, p153 (2 lines) p17 : p174, p175 (2 lines) p22 : p220, p221, p225 (3 lines) port function the input/output ports can be set for input or output mode bitwise by using the input/output port ___ direction control register. (however, p64 is an sbi input-only port, and p221 is can input-only port.) pin function dual-functions shared with peripheral i/o or external extended signals (or multi-functions shared with peripheral i/os which have multiple functions.) pin function p0 - p4 : changed by setting cpu operation mode (mod0 and mod1 pins) changeover p6 - 22 : changed by setting the input/output port operation mode register. (however, peripheral i/o pin functions are selected using the peripheral i/o register.) note: input/output ports p14, p16, and p18-p21 do not exist. table 10 cpu operation modes and p0-p4 pin functions mod0 mod1 operation mode pin functions of p0-p4 vss vss single-chip mode input/output port pin vss vcce external extended mode vcce vss processor mode (fp pin = vss) vcce vcce reserved (use inhibited) C note: vcce connects to +5v or +3.3v, and vss connects to gnd. each input/output port is a dual-function pin shared with otherinternal peripheral i/o or external extended bus signal lines. these pin functions are selected by using the chip op- eration mode select or the input/output port operation mode registers. these input/output ports are interfaced using a dedicated power supply to allow for connections to the pe- ripheral circuits operating with 5v or 3.3v. external extended signal pin
mitsubishi microcomputers 19 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group figure 10 input/output ports and pin function assignments p0 p1 p2 p3 p4 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p5 db0 02 57 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 a23 a24 a25 a26 a27 a28 a29 a30 a15 a16 a17 a18 a19 a20 a21 a22 blw/ble rd cs0 cs1 a13 a14 sbi bclk/ wr wait hreq hack rtdtxd rtdrxd rtdack rtdc lk txd0 rxd0 sclki 0/ sclko 0 txd1 rxd1 sclki 1/ sclko 1 to 16 t o 17 to 18 t o 19 to 20 to 11 t o 12 to 13 t o 14 to 15 to 10 to 9 to 8 to 3 to 4 to 5 to 6 to 7 to 2 to 1 to 0 tclk 0 tclk 1 tclk 2 tclk 3 ti n 16 ti n 17 ti n 18 ti n 19 ti n 20 ti n 21 ti n 22 ti n 23 tin 0 tin 3 cpu operation mode settings (note1) (reserved) input/output port operation mode register settings note 1: the pin function are selected by setting the mod0 and mod1 pins. note 2: p14, p16, p18, p19, p20, and p21 do not exist. p16 p17 txd 2 r xd 2 p18 p19 p20 p21 p22 ctx c rx a1 2 bhw/bhe 13 4 6 (p61) (p62) (p63)
mitsubishi microcomputers 20 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group item content number of channels 10 channels transfer request ? software trigger ? request from internal peripheral i/o: a-d converter, multijunction timer, or serial i/o (reception completed, transmit buffer empty) ? cascaded connection between dma channels possible (note) maximum number of times transferred256 times transferable address space ? 64 kbytes (address space from h0080 0000 to h0080 ffff) ? transfers between internal peripheral i/os, between internal ram and internal peripheral io, and between internal rams are supported transfer data size 16 bits or 8 bits transfer method single transfer dma (control of the internal bus is relinquished for each transfer performed), dual-address transfer transfer mode single transfer mode direction of transfer one of three modes can be selected for the source and destination of transfer: ? address fixed ? address increment ? 32-channel ring buffer channel priority channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (fixed priority) maximum transfer rate 13.3 mbytes per second (when internal peripheral clock = 20 mhz) interrupt request group interrupt request can be generated when each transfer count register underflows transfer area 64 kbytes from h0080 0000 to h0080 ffff (transfer is possible in the entire internal ram/sfr area) note: the following dma channels can be cascaded. dma transfer on channel 1 started at end of one dma transfer on channel 0 dma transfer on channel 2 started at end of one dma transfer on channel 1 dma transfer on channel 0 started at end of one dma transfer on channel 2 dma transfer on channel 4 started at end of one dma transfer on channel 3 dma transfer on channel 6 started at end of one dma transfer on channel 5 dma transfer on channel 7 started at end of one dma transfer on channel 6 dma transfer on channel 5 started at end of one dma transfer on channel 7 dma transfer on channel 9 started at end of one dma transfer on channel 8 dma transfer on channel 5 started at end of all dma transfers on channel 0 (underflow of transfer count register) built-in 10-channel dmac the microcomputer contains 10 channels of dmac, allowing for data transfer between internal peripheral i/os, between internal ram and internal peripheral i/o, and between inter- nal rams. dma transfer requests can be issued from the user-cre ated software, as well as can be triggered by a signal gener- ated by the internal peripheral i/o (a-d converter, mjt, or serial i/o). table 11 outline of the dmac the microcomputer also supports cascaded connection be- tween dma channels (starting dma transfer on a channel at end of transfer on another channel). this makes advanced transfer processing possible without causing any additional cpu load.
mitsubishi microcomputers 21 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group figure 11 block diagram of the dmac dma request selector a-d conversion completed dma channel 0 software start one dma0 transfer completed internal bus software start software start serial i/o0 (reception completed) one dma2 transfer completed one dma3 transfer completed mjt (tio8_udf) mjt (input event bus 2) mjt (output event bus 0) mjt (tin19 input signal) software start mjt (tin18 input signal) one dma1 transfer completed mjt (output event bus 1) software start serial i/o0 (transmit buffer empty) serial i/o1 (reception completed) source destination determination block dma start mjt (tin0 input signal) all dma0 transfers completed (udf) software start one dma5 transfer completed software start one dma7 transfer completed serial i/o2 (reception completed) mjt (tin20 input signal) serial i/o1 (transmit buffer empty) software start one dma6 transfer completed serial i/o2 (transmit buffer empty) software start mjt (input event bus 0) source destination transfer count interrupt request internal bus arbitration software start one dma8 transfer completed transfer count udf dma request selector dma channel 1 udf source destination transfer count dma request selector dma channel 2 udf source destination transfer count dma request selector dma channel 3 udf source destination transfer count dma request selector dma channel 4 udf source destination transfer count dma request selector dma channel 5 udf source destination transfer count dma request selector dma channel 6 udf source destination transfer count dma request selector dma channel 7 udf source destination transfer count dma request selector dma channel 8 udf source destination transfer count dma request selector dma channel 9 udf determination block dma start internal bus arbitration interrupt request
mitsubishi microcomputers 22 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group built-in 37-channel multijunction timers (mjt) the microcomputer contains a total of 37 channels of multijunction timers consisting of 11 channels of 16-bit out- put related timers, 10 channels of 16-bit input/output related timers, eight channels of 16-bit input related timers, eight channels of 32-bit input related timers, each timer has mul- tiple operation modes to choose from, depending on the pur- poses of use. also, the maltijunction timers internally have a clock bus, in- put event bus, and an output event bus, so that multiple tim- ers can be used in combination allowing for a flexible timer configuration. the output related timers have a correcting function that allows the timers count value to be incremented or decremented as necessary while count is in progress, mak- ing real time output control possible. figure 12 conceptual diagram of the multijunction timer (mjt) timer clk en e/ l prs clock bus input event bus e/l timer clk en interrupt output interrupt output output event bus f/f to pin tin pin tclk pin note: this is a conceptual diagram and does not show the actual timer configuration. e/l prs : edge/level selector : prescaler : junction box (selector) : output flip-flop f/ f to dmac, a-d converter f/f to pin output related timer : 11ch input/output related timer : 10ch 16-bit input related timer : 8ch 32-bit input related timer : 8ch 1/2 internal peripheral clock
mitsubishi microcomputers 23 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group table 12 outline of multijunction timers name type number of channels content top output-related 11 one of three input modes can be selected in software. (timer output) 16-bit timer < with correction function > (down-counter) ? single-shot output mode ? delayed single-shot output mode < without correction function > ? continuous output mode tio input/output-related 10 one of three input modes or four output modes can be (timer 16-bit timer selected by software. input output) (down-counter) < input modes > ? measure clear input mode ? measure free-run input mode ? noise processing input mode < output mode without correction function ? pwm output mode ? single-shot output mod ? delayed single-shot output mode ? continuous output mode tms input-related8 16-bit input measure timer. (timer 16-bit timer measure small) (up counter) tml input-related8 32-bit input measure timer. (timer 32-bit timer measure large) (up counter)
mitsubishi microcomputers 24 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group figure 13 block diagram of multijunction timers (mjt) (1/3) irq2 irq1 2 clk en udf top 0 clk en udf top 1 clk en udf top 2 clk en udf top 3 tclk0s to 0 irq 9 3 2 1 0 clk en udf top 4 clk en udf top 5 tclk 0 tin 0 tclk1 s s tin0 s clk en udf top 6 clk en udf top 7 s s s s s clk en udf top 8 clk en udf top 9 clk en udf top 10 clk en/ cap udf tio 0 clk en/ cap udf tio 1 clk en/ cap udf tio 2 clk en/ cap udf tio 3 clk en/ cap udf tio 4 s s tin3 s s s s prs 1 prs 0 clk en/ cap udf tio 5 s s tclk2 clk en/cap udf tio 6 s s clk en/ cap udf tio 7 s s s s clk en/ cap udf tio 8 clk en/ cap udf tio 9 s s f/ f0 f/ f1 f/ f2 f/ f3 f/ f4 f/ f5 f/ f6 f/ f7 f/ f8 f/ f9 f/f1 0 f/f1 1 f/f1 2 f/f1 3 f/f1 4 f/f1 5 s f/f1 6 f/f1 7 f/f1 8 f/f1 9 f/f2 0 s : selector f/f : output flip-flop psc0-2 : prescaler s s s s s s s s s s s s s s irq2 irq2 irq2 irq2 irq2 to 1 to 2 to 3 to 4 to 5 to 6 to 7 to 8 to 9 to 10 to 11 to 12 to 13 to 14 to 15 irq1 irq1 irq6 irq6 irq5 irq0 irq0 irq0 irq0 irq4 to 16 to 17 to 18 to 19 to 20 irq4 drq0 irq3 irq3 3 2 1 0 0 1 2 3 3 2 1 0 3 2 1 0 prs 2 irq4 irq4 0 1 2 3 tin3 s tclk1 s tclk2 s drq 7 clock bus input event bus output event bus 1 /2 internal peripheral clock
mitsubishi microcomputers 25 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group figure 14 block diagram of multijunction timers (mjt) (2/3) 3 2 1 0 3 2 1 0 clk tms 0 ovf cap3 cap2 cap1 cap0 s clk tml 0 cap3 cap2 cap1 cap0 s s s s tin20 tin2 1 tin2 2 tin2 3 irq11 irq11 irq11 irq11 0 1 2 3 irq 7 3 2 1 0 3 2 1 0 0 1 2 3 tin20 s tin21 s tin22 s tin23 s s drq12 clk tms 1 ovf cap3 cap2 cap1 cap0 s s s s s drq5 tin16 tin1 7 tin1 8 tin19 drq6 irq10 irq10 irq10 irq10 irq 7 tin16 s tin17 s tin18 s tin19 s (note1) clk tml 1 cap3 cap2 cap1 cap0 s tclk3 tclk3 s s s s s s s s s ad0trg (to a-d0 converter) clock bus input event bus output event bus 1/2 internal peripheral clock 1/2 internal peripheral clock
mitsubishi microcomputers 26 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group figure 15 block diagram of multijunction timers (mjt) (3/3) 3 2 1 0 3 2 1 0 0 1 2 3 3 2 1 0 3 2 1 0 0 1 2 3 tio8-udf s dma 0 dmairq 0 s dma 1 dmairq 0 s dma 2 dmairq 0 tin18 s dma 3 dmairq 0 s dma 4 dmairq 0 tin19 sio0-txd sio1-rxd sio0-rxd s dma 5 dmairq 1 s dma 6 dmairq 1 sio2- rxd sio1- txd s dma 7 dmairq 1 dmairq 1 sio2- txd s dma 9 dmairq 1 tin20 tin0 dma 8 udf s ad0 completed clock bus input event bus output event bu s end udf end udf end udf end udf end udf end udf end udf end udf udf
mitsubishi microcomputers 27 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group built-in two independent a-d converters the microcomputer contains two 16-channel converters with 10-bit resolution (a-d0 converter and a-d1 converter). in addition to single conversion on each channel, continuous a-d conversion on a combined group of 4, 8, and 16 chan- nels is possible. the a-d converted value can be read out in either 10 bits or 8 bits. table 13 outline of the a-d converters item content analog input 16 channels a-d conversion methods uccessive approximation method. resolution 10 bits (conversion results can be read out in either 10 or 8 bits.) absolute accuracy normal rate mode + 2 lsb (conditions: ta = -40 ~ +125 c, double rate mode + 2 lsb avcc0 = vref0 = 5.12v) (note 1) conversion mode a-d conversion mode,comparator mode operation mode single mode, scan mode scan mode single -shot scan mode, continuous scan mode. conversion start trigger software start started by setting a-d conversion start bit to 1. hardware start a-d0 converter started by mjt output event bus 3. conversion rate during single mode normal 299 1/ f (bclk) f(bclk) : internal peripheral clock (shortest time ) double speed173 1/ f (bclk) (note 2) operating frequency during comparator mode normal 47 1/ f (bclk) (shortest time ) double speed29 1/ f (bclk) interrupt request generation when a-d conversion is finished, when comparate operation is finished, when single-shot scan is finished, or when one cycle of continuous scan is finished. dma transfer request generation when a-d conversion is finished, when comparate operation is finished, when single-s hot scan is finished, or when one cycle of continuous scan is finished. note 1: the rated value of conversion accuracy here is that of the microcomputer's own as a single unit which can be exhibited when the microcomputer is used in an environment where it may not be affected by the power supply wiring or noise on the boa rd. note 2: when input clock (xin) = 10 mhz, f(bclk) = 20 mhz. in addition to ordinary a-d conversion, the converters sup- port comparator mode in which the set value and a-d con- verted value are compared to determine which is larger or smaller than the other. when a-d conversion is finished, the converters can generated a dma transfer request, as well as an interrupt. the a-d converters are interfaced using a dedicated power supply to allow for connections to the peripheral circuits op- erating with 5v or 3.3v.
mitsubishi microcomputers 28 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group figure 16 block diagram of the a-d0 converter ad0in0 ad0in1 ad0in2 ad0in3 ad0in4 ad0in5 ad0in6 ad0in7 selector interrupt request avss0 vref0 10-bit a-d successive approximation register (ad0sar) 10-bit a-d0 data register 0 10-bit a-d0 data register 1 single mode register a-d comparate data register a-d control circuit ? mode selection ? channel selection ? conversion time selection ? flag control ? interrupt control 10-bit d-a converter comparator ad0in8 ad0in9 ad0n10 ad0in11 ad0in12 ad0in13 ad0in14 ad0in15 ad0cmp ad0dt0 ad0dt1 ad0dt2 ad0dt3 ad0dt4 ad0dt5 ad0dt6 ad0dt7 ad0dt8 ad0dt9 ad0dt10 ad0dt11 ad0dt12 ad0dt13 ad0dt14 ad0dt15 dma transfer request successive approximation -type a-d converter unit internal data bus scan mode register ad0scm0,1 ad0sim0,1 avcc0 output event bus 3 (multijunction timer) 10-bit readout 8-bit readout shifter 10-bit a-d0 data register 2 10-bit a-d0 data register 3 10-bit a-d0 data register 4 10-bit a-d0 data register 5 10-bit a-d0 data register 6 10-bit a-d0 data register 7 10-bit a-d0 data register 8 10-bit a-d0 data register 9 10-bit a-d0 data register 10 10-bit a-d0 data register 11 10-bit a-d0 data register 12 10-bit a-d0 data register 13 10-bit a-d0 data register 14 10-bit a-d0 data register 15
mitsubishi microcomputers 29 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group 3-channel high-speed serial i/os the microcomputer contains three channels of serial i/os consisting of two channels that can be set for csio mode (clock-synchronized serial i/o) or uart mode (asynchro- nous serial i/o) and one other channel that can only be set for uart mode. the sio has the function to generate a dma transfer re- quest when data reception is completed or the transmit reg- ister becomes empty, and is capable of high-speed serial communication without causing any additional cpu load. table 14 outline of serial i/o item content number of channels csio/uart: 2 channels (sio0,sio1) uart only : 1 channels (sio2) clock during csio mode : internal clock / external clock, selectable (note1) during uart mode : internal clock only transfer mode transmit half-duplex, receive half-duplex, transmit/receive full-duplex brg count sourcef (bclk), f(bclk)/8, f(bclk)/32, f(bclk)/256 (when internal clock is selected) (note2) data format csio mode : data length = fixed to 8 bits order of transfer = fixed to lsb first uartmode : start bit = 1 bit character length = 7, 8, or 9 bits parity bit = added or not added (when added, selectable between odd and even parity) stop bit = 1 or 2 bits order of transfer = fixed to lsb first baud rate csio mode : 152 bits per second to 2 mbits per second (when operating with f(bclk) = 20 mhz) uartmode : 19 bits per second to 156 kbits per second (when operating with f(bclk) = 20 mhz) error detection csio mode : overrun error only uartmode : overrun, parity, and framing errors (the error-sum bit indicates which error has occurred) fixed cycle clock when using sio0 and sio1 as uart, this function outputs a divided-by-2 brg clock from the sclk pin. output function note 1: during csio mode, the maximum input frequency of an external clock is f(bclk) divided by 16. note 2: when f(bclk) is selected for the brg count source, the brg set value is subject to limitations.
mitsubishi microcomputers 30 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group figure 17 block diagram of serial i/o sclki0/ sclko0 bclk, bclk/8, bclk/32, bclk/256 baud rate generator (brg) bclk (set value + 1) 1 internal data bus csio mode when internal clock selected when uart mode selected csio mode uart mode when internal clock selected 1/16 1/2 clock divider rxd0 txd0 receive interrupt transmit/receive control circuit sio0 transmit buffer register sio0 transmit shift register receive dma transfer request transmit interrupt transmit dma transfer request to dma3 sio0 receive shift register sio0 receive buffer register when external clock selected sio0 sio1 sio2 rxd1 txd1 sio1 transmit shift register sio1 receive shift register rxd2 txd2 to interrupt controller to dma4 receive interrupt transmit/receive control circuit receive dma transfer request transmit interrupt transmit dma transfer request sclki1/ sclko1 to dma6 to interrupt controller to dma3 sio2 transmit shift register sio2 receive shift register receive interrupt transmit/receive control circuit receive dma transfer request transmit interrupt transmit dma transfer request to dma7 to dma5 to interrupt controller note 1 : when bclk is selected, the brg set value is subject to limitations. note 2 : sio2 does not have the sclki/sclko function.
mitsubishi microcomputers 31 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group can module the m32171 group contains two full can modules compli- ant with can specification v2.0b (can0 and can1), each of which has 16-channel message slots and three mask reg- isters. figure 18 block diagram of the can module ctx crx can0 protocol controller 2.0b active can0 message slot 0-15 control register can0 global mask register can0 local mask register a can0 local mask register b can0 extended register message memory acceptance filtering 16-bit timer can0 time stamp register can0 configuration register can0 slot status register can0 slot interrupt control register can0 rec register can0 tec register can0 error interrupt control register interrupt control circuit can0 transmit/receive & error interrupt data bus (1) message id (2) data length code (3) message data (4) time stamp can0 status register can0 control register
mitsubishi microcomputers 32 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group 8-level interrupt controller the interrupt controller controls interrupt requests from each internal peripheral i/o (31 sources) by using eight pri- ority levels assigned to each interrupt source, including in- terrupts disabled. in addition to these interrupts, it handles system break interrupt (sbi), reserved instruction excep- tion (rie), and address exception (ae) as nonmaskable in- terrupts. wait controller the wait controller supports access to external devices. for access to an external extended area of up to 1 mbytes (during external extended or processor mode), the wait controller controls bus cycle extension by inserting one to ____ four wait cycles or using external wait signal input. real-time debugger (rtd) rtdclk rtdrxd rtdtxd rtdac k command address data internal ram (16kb) m32r cpu M32171F4VFP, m32171f3vfp, m32171f2vfp data data data bus(cpu ) data bus(rtd) r/w without cpu intervention virtual-dpram structure figure 19 conceptual diagram of the realtime debugger (rtd) realtime debugger (rtd) the realtime debugger (rtd) provides a function for ac- cessing directly from the outside to the internal ram. it uses a dedicated clock-synchronized serial i/o to communicate with the outside. use of the rtd communicating via dedicated serial lines al- lows the internal ram to be read out and rewritten without having to halt the cpu.
mitsubishi microcomputers 33 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group cpu instruction set the m32r employs a risc architecture, supporting a total of 83 discrete instructions. (1) load/store instructions perform data transfer between memory and registers. ld load ldb load byte ldub load unsigned byte ldh load halfword lduh load unsigned halfword lock load locked st store stb store byte sth store halfword unlock store unlocked (2) transfer instructions perform register to register transfer or register to immediate transfer . ld24 load 24-bit immediate ldi load immediate mv move register mvfc move from control register mvtc move to control register seth set high-order 16-bit (3) branch instructions used to change the program flow. bc branch on c-bit beq branch on equal beqz branch on equal zero bgez branch on greater than or equal zero bgtz branch on greater than zero bl branch and link blez branch on less than or equal zero bltz branch on less than zero bnc branch on not c-bit bne branch on not equal bnez branch on not equal zero bra branch jl jump and link jmp jump nop no operation (4) arithmetic/logic instructions perform comparison, arithmetic/logic operation, multiplica- tion/division, or shift between registers. ? comparison cmp compare cmpi compare immediate cmpu compare unsigned cmpui compare unsigned immediate ? logical operation and and and3 and 3-operand not logical not or or or3 or 3-operand xor exclusive or xor3 exclusive or 3-operand ? arithmetic operation add add add3 add 3-operand addi add immediate addv add (with overflow checking) addv3 add 3-operand addx add with carry neg negate sub subtract subv subtract (with overflow checking) subx subtract with borrow ? multiplication/division div divide divu divide unsigned mul multiply rem remainder remu remainder unsigned ? shift sll shift left logical sll3 shift left logical 3-operand slli shift left logical immediate sra shift right arithmetic sra3 shift right arithmetic 3-operand srai shift right arithmetic immediate srl shift right logical srl3 shift right logical 3-operand srli shift right logical immediate (5) instructions for the dsp function perform 32 bit 16 bit or 16 bit 16 bit multiplication or sum- of-products calculation. these instructions also perform rounding of the accumulator data or transfer between accu- mulator and general-purpose register. machi multiply-accumulate high-order halfwords maclo multiply-accumulate low-order halfwords macwhi multiply-accumulate word and high-order halfword macwlo multiply-accumulate word and low-order halfword mulhi multiply high-order halfwords mullo multiply low-order halfwords mulwhi multiply word and high-order halfword mulwlo multiply word and low-order halfword mvfachi move from accumulator high-order word mvfaclo move from accumulator low-order word mvfacmi move from accumulator middle-order word mvtachi move to accumulator high-order word mvtaclo move to accumulator low-order word rac round accumulator rach round accumulator halfword (6) eit related instructions start trap or return from eit processing. rte return from eit trap trap
mitsubishi microcomputers 34 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32171 group figure 20 instructions for the dsp function rsrc1 0151631 hl 0151631 h l maclo instruction machi instruction rsrc2 acc 63 + 63 acc rsrc1 031 32 bit 0151631 h l macwlo instruction macwhi instruction rsrc2 acc 63 63 acc rsrc1 0151631 h acc 63 l 0151631 h l mullo instruction mulhi instruction rsrc 2 rsrc1 031 acc 63 0151631 hl mulwlo instruction mulwhi instruction rsrc2 32 bit 63 ac c rac instruction 63 ac c rach instruction < ropund off instruction > sign 0 data sign 0 data 63 63 rdest 1 63 15 16 31 32 47 48 mvfachi instruction ac c mvfaclo instruction mvfacmi instruction rsrc 031 63 31 32 ac c mvtaclo instruction mvtachi instruction < multiply instruction > < multiply-accumulate instruction > < accumulator - register transfer instruction > + + + 0 0 0 0 0 0 0 0 0 0 0 0 0
mitsubishi microcomputers 35 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32171 group package dimensions diagram lqfp144-p-2020-0.50 weight(g) C jedec code eiaj package code lead material cu alloy 144p6q-a plastic 144pin 20 ? 20mm body lqfp C 0.125 C CC 0.2 C C CC C C C C C symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 C C i 2 1.0 C C m d 20.4 C C m e 20.4 8 0 0.1 1.0 0.65 0.5 0.35 22.2 22.0 21.8 22.2 22.0 21.8 0.5 20.1 20.0 19.9 20.1 20.0 19.9 0.175 0.125 0.105 0.27 0.22 0.17 1.4 0.05 1.7 e recommended mount pad m d l 2 b 2 m e e a h d d h e e 1 36 37 72 73 108 109 144 f b e l a 2 a 1 l 1 c detail f y
single-chip 32-bit cmos microcomputer mitsubishi microcomputers 2001-5-14 rev.1.0 32171 group head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan ? 2001 mitsubishi electric corp. new publication, effective may 2001. specifications subject to change without notice. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein.
rev. revision description rev. no. page point date 1.0 first edition 010514 revision description list 32171group data sheet (1/1)

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